 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LTC3414 4A, 4MHz, Monolithic Synchronous Step-Down Regulator FEATURES s s s s s s s s s DESCRIPTIO s s s s s High Efficiency: Up to 95% 4A Output Current Low Quiescent Current: 64A Low RDS(ON) Internal Switch: 67m Programmable Frequency: 300KHz to 4MHz 2.25V to 5.5V Input Voltage Range 2% Output Voltage Accuracy 0.8V Reference Allows Low Output Voltage Selectable Forced Continuous/Burst Mode(R)operation with Adjustable Burst Clamp Synchronizable Switching Frequency Low Dropout Operation: 100% Duty Cycle Power Good Output Voltage Monitor Overtemperature Protected Available in 20-Lead Exposed TSSOP Package The LTC(R)3414 is a high efficiency monolithic synchronous, step-down DC/DC converter utilizing a constant frequency, current mode architecture. It operates from an input voltage range of 2.25V to 5.5V and provides a regulated output voltage from 0.8V to 5V while delivering up to 4A of output current. The internal synchronous power switch with 67m on-resistance increases efficiency and eliminates the need for an external Schottky diode. Switching frequency is set by an external resistor or can be synchronized to an external clock. 100% duty cycle provides low dropout operation extending battery life in portable systems. OPTI-LOOP(R) compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The LTC3414 can be configured for either Burst Mode operation or forced continuous operation. Forced continuous operation reduces noise and RF interference while Burst Mode operation provides high efficiency by reducing gate charge losses at light loads. In Burst Mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the requirements of the application. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s Point-of-Load Regulation Notebook Computers Portable Instruments Distributed Power Systems TYPICAL APPLICATIO VIN 2.7V TO 5.5V PVIN SVIN 2.2M 294k RT 22F 100 95 PGOOD LTC3414 SW RUN/SS PGND SGND VFB COUT* 0.47H VOUT 2.5V AT 4A 90 LTC3414 Efficiency Curve Burst Mode OPERATION EFFICIENCY (%) 85 80 75 70 65 60 FORCED CONTINUOUS 1000pF RITH* 470pF ITH SYNC/MODE 110k 75k 392k 3414 F01a 55 50 0.001 0.01 0.1 1.0 LOAD CURRENT (A) 10 3414 F01b *BURST MODE OPERATION: COUT = 470F SANYO POSCAP 4TPB470M, RITH = 20k FORCED CONTINUOUS: COUT = (2) 100F TDKC4532X5ROJ107M, RITH = 12.1k Figure 1. 2.5V/4A Step-Down Regulator 3414f U U U 1 LTC3414 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW PGND 1 RT 2 SYNC/MODE 3 RUN/SS 4 SGND 5 NC 6 PVIN 7 SW 8 SW 9 PGND 10 21 20 PGND 19 VFB 18 ITH 17 PGOOD 16 SVIN 15 NC 14 PVIN 13 SW 12 SW 11 PGND Input Supply Voltage ................................... -0.3V to 6V ITH, RUN/SS, VFB, SYNC/MODE Voltages .................................. -0.3 to VIN SW Voltages ................................. -0.3V to (VIN + 0.3V) Peak SW Sink and Source Current ......................... 9.5A Operating Ambient Temperature Range (Note 2) .............................................. - 40C to 85C Junction Temperature (Notes 5, 6) ....................... 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C ORDER PART NUMBER LTC3414EFE FE PACKAGE 20-LEAD PLASTIC TSSOP EXPOSED PAD (PIN 21) MUST BE SOLDERED TO PCB TJMAX = 125C, JA = 38C/W, JC = 10C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.3V unless otherwise specified. SYMBOL VIN IFB VFB VFB VLOADREG VPGOOD RPGOOD IQ PARAMETER Input Voltage Range Feedback Pin Input Current Regulated Feedback Voltage Reference Voltage Line Regulation Output Voltage Load Regulation Power Good Range Power Good Resistance Input DC Bias Current Active Current Sleep Shutdown Switching Frequency Switching Frequency Range SYNC Capture Range RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET Peak Current Limit Undervoltage Lockout Threshold SW Leakage Current RUN Threshold CONDITIONS q ELECTRICAL CHARACTERISTICS MIN 2.25 0.784 TYP (Note 3) (Note 3) VIN = 2.7V to 5.5V (Note 3) Measured in Servo Loop, VITH = 0.36V Mesured in Servo Loop, VITH = 0.84V q q q q 0.800 0.04 0.02 -0.02 7.5 120 250 64 0.02 1.00 MAX 5.5 0.2 0.816 0.2 0.2 -0.2 9 200 330 100 1 1.12 4 4 100 100 2.25 1.0 0.8 UNITS V A V %V % % % A A A MHz MHz MHz m m A V A V fOSC fSYNC RPFET RNFET ILIMIT VUVLO ILSW VRUN (Note 4) VFB = 0.75V, VITH = 1.2V VFB = 1V, VITH = 0V, VSYNC/MODE = 0V VRUN = 0V ROSC = 294k 0.88 0.3 0.3 ISW = 300mA ISW = -300mA 6 1.75 VRUN = 0V, VIN = 5.5V 0.5 67 50 8 2.00 0.1 0.65 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3414E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating ambient temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The LTC3414 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH). Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: TJ =TA + (PD)(38C/W) Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliabiability. 3414f 2 U W U U WW W LTC3414 TYPICAL PERFOR A CE CHARACTERISTICS VREF vs Temperature, VIN = 3.3V 0.800 90 80 0.799 ON-RESISTANCE (m) ON-RESISTANCE (m) VREF (V) 0.798 0.797 0.796 0.795 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) 3414 G01 Switch Leakage vs Input Voltage 20 18 SWITCH LEAKAGE CURRENT (nA) TA = 25C 16 FREQUENCY (kHz) 12 10 8 6 4 2 0 2.25 NFET PFET FREQUENCY (kHz) 14 2.75 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) Frequency vs Temperature 1090 1070 1050 FREQUENCY (kHz) MINIMUM PEAK INDUCTOR CURRENT (A) VIN = 3.3V ROSC = 294k QUIESCENT CURRENT (A) 1030 1010 990 970 950 930 910 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 3414 G07 UW 5.25 3414 G04 Switch On-Resistance vs Input Voltage 120 TA = 25C PFET Switch On-Resistance vs Temperature, VIN = 3.3V 100 80 PFET 60 40 20 NFET 70 60 50 40 30 20 10 NFET 0 2.25 2.75 3.25 3.75 4.25 4.75 5.25 INPUT VOLTAGE (V) 5.75 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 3414 G03 3414 G02 Frequency vs ROSC 7000 6000 5000 4000 3000 2000 1000 0 25 125 225 325 425 525 625 725 825 925 ROSC (k) 3414 G05 Frequency vs Input Voltage VIN = 3.3V TA = 25C 1040 1020 1000 980 960 940 920 900 2.25 ROSC = 294k TA = 25C 2.75 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 5.25 3414 G06 DC Supply Current vs Input Voltage 350 300 ACTIVE 250 200 150 100 SLEEP 50 0 2.25 TA = 25C 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 Minimum Peak Inductor Current vs Burst Clamp Voltage VIN = 3.3V TA = 25C 2.75 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 5.25 3414 G08 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 BURST CLAMP VOLTAGE (V) 0.8 3414 G09 3414f 3 LTC3414 TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Load Current, Burst Mode Operation 100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0.001 0.01 0.1 1 LOAD CURRENT (A) 10 3414 G10 VIN = 3.3V VIN = 5V EFFICIENCY (%) 60 50 40 30 20 10 0 0.001 EFFICIENCY (%) Efficiency vs Input Voltage 98 96 94 92 EFFICIENCY (%) 90 88 86 84 82 80 78 2.5 3.0 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0 5.5 3414 G13 IOUT = 1A VOUT = 2.5V TA = 25C L = 0.2H 85 80 75 70 300 800 1300 1800 2300 2800 3300 3800 FREQUENCY (kHz) 3414 G14 IOUT = 4A VOUT/VOUT (%) EFFICIENCY (%) Burst Mode Operation OUTPUT VOLTAGE 20mV/DIV OUTPUT VOLTAGE 100mV/DIV INDUCTOR CURRENT 500mA/DIV VIN = 3.3V, VOUT = 2.5V LOAD = 250mA 4 UW TA = 25C Efficiency vs Load Current, Forced Continuous 100 VOUT = 2.5V 90 TA = 25C 80 70 VIN = 3.3V VIN = 5V 100 95 90 85 80 75 70 65 60 55 0.01 0.1 1 LOAD CURRENT (A) 10 3414 G11 Efficiency vs Load Current Burst Mode OPERATION TA = 25C FORCED CONTINUOUS VIN = 3.3V VOUT = 2.5V 0.01 0.1 1 LOAD CURRENT (A) 10 3414 G12 50 0.001 Efficiency vs Frequency 100 L = 1H 95 L = 0.47H 90 -0.10 -0.15 -0.20 -0.25 -0.30 VIN = 3.3V VOUT = 2.5V TA = 25C 0 -0.05 Load Regulation VIN = 3.3V VOUT = 2.5V TA = 25C 0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (A) 3.5 4.0 3414 G15 Load Step Transient Forced Continuous INDUCTOR CURRENT 2A/DIV 10s/DIV 3414 G16 20s/DIV VIN = 3.3V, VOUT = 2.5V LOAD STEP = 0A TO 4A 3414 G17 3414f LTC3414 TYPICAL PERFOR A CE CHARACTERISTICS Load Step Transient Burst Mode Operation OUTPUT VOLTAGE 100mV/DIV VRUN OUTPUT VOLTAGE INDUCTOR CURRENT 2A/DIV VIN = 3.3V, VOUT = 2.5V LOAD STEP = 250mA TO 4A PI FU CTIO S PGND (Pins 1, 10, 11, 20): Power Ground. Connect this pin closely to the (-) terminal of CIN and COUT. RT (Pin 2): Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the switching frequency. SYNC/MODE (Pin 3): Mode Select and External Clock Synchronization Input. To select Forced Continuous, tie to SVIN. Connecting this pin to a voltage between 0V and 1V selects Burst Mode operation with the burst clamp set to the pin voltage. RUN/SS (Pin 4): Run Control and Soft-Start Input. Forcing this pin below 0.5V shuts down the LTC3414. In shutdown all functions are disabled. Less than 1A of supply current is consumed. A capacitor to ground from this pin sets the ramp time to full output current. SGND (Pin 5):Signal Ground. All small signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. NC (Pin 6): Open. No internal connection. PVIN (Pins 7, 14): Power Input Supply. Decouple this pin to PGND with a capacitor. SW (Pins 8, 9, 12, 13): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. NC (Pin 15): Open. No internal connection. SVIN (Pin 16): Signal Input Supply. Decouple this pin to SGND with a capacitor. PGOOD (Pin 17): Power Good Output. Open drain logic output that is pulled to ground when the output voltage is not within 7.5% of regulation point. ITH (Pin 18): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is from 0.2V to 1.4V with 0.4V corresponding to the zero-sense voltage (zero current). VFB (Pin 19): Feedback Pin. Receives the feedback voltage from a resistive divider connected across the output. Exposed Pad (Pin 21): Should be connected to SGND and soldered to the PCB. UW Start-Up Transient INDUCTOR CURRENT 2A/DIV 20s/DIV 3414 G18 1ms/DIV VIN = 3.3V, VOUT = 2.5V LOAD = 4A 3414 G19 U U U 3414f 5 LTC3414 BLOCK DIAGRA W SVIN 16 SGND 5 ITH 18 EXPOSED PAD 21 PVIN 7 PVIN 14 0.8V VOLTAGE REFERENCE SLOPE COMPENSATION RECOVERY BCLAMP PMOS CURRENT COMPARATOR + - + VFB 19 - + V SYNC/MODE 0.74V + OSCILLATOR 8 9 LOGIC NMOS CURRENT COMPARATOR SW SW - - RUN/SS 4 RUN + 0.86V PGOOD 17 - CURRENT REVERSAL COMPARTOR 2 RT 3 SYNC/MODE OPERATIO Main Control Loop The LTC3414 is a monolithic, constant-frequency, current-mode step-down DC/DC converter. During normal operation, the internal top power switch (P-channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the current comparator trips and turns off the top power MOSFET. The peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ITH pin. The error amplifier adjusts the voltage on the ITH pin by comparing the feedback signal from a resistor divider on the VFB pin with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the ITH voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-channel MOSFET) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. The bottom current limit is set at -5A for forced continuous mode and 0A for Burst Mode operation. The operating frequency is externally set by an external resistor connected between the RT pin and ground. The practical switching frequency can range from 300kHz to 4MHz. Overvoltage and undervoltage comparators will pull the PGOOD output low if the output voltage comes out of regulation by 7.5%. In an overvoltage condition, the top power MOSFET is turned off and the bottom power MOSFET is switched on until either the overvoltage condition clears or the bottom MOSFET's current limit is reached. Forced Continuous Mode Connecting the SYNC/MODE pin to SVIN will disable Burst Mode operation and force continuous current operation. At light loads, forced continuous mode operation is less efficient than Burst Mode operation, but may be desirable in some applications where it is necessary to keep switch3414f 6 + + BURST COMPARATOR ERROR AMPLIFIER - SLOPE COMPENSATION 12 SW 13 SW 1 PGND + 10 PGND - 20 PGND 11 PGND 3414 BD U LTC3414 OPERATIO ing harmonics out of a signal band. The output voltage ripple is minimized in this mode. Burst Mode Operation Connecting the SYNC/MODE pin to a voltage in the range of 0V to 1V enables Burst Mode operation. In Burst Mode operation, the internal power MOSFETs operate intermittently at light loads. This increases efficiency by minimizing switching losses. During Burst Mode operation, the minimum peak inductor current is externally set by the voltage on the SYNC/MODE pin and the voltage on the ITH pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. When the average inductor current is greater than the load current, the voltage on the ITH pin drops. As the ITH voltage falls below 150mV, the burst comparator trips and enables sleep mode. During sleep mode, the top power MOSFET is held off and the ITH pin is disconnected from the output of the error amplifier. The majority of the internal circuitry is also turned off to reduce the quiescent current to 64A while the load current is solely supplied by the output capacitor. When the output voltage drops, the ITH pin is reconnected to the output of the error amplifier and the top power MOSFET along with all the internal circuitry is switched back on. This process repeats at a rate that is dependent on the load demand. Pulse Skipping operation is implemented by connecting the SYNC/MODE pin to ground. This forces the burst clamp level to be at 0V. As the load current decreases, the peak inductor current will be determined by the voltage on the ITH pin until the ITH voltage drops below 400mV. At this point, the peak inductor current is determined by the minimum on-time of the current comparator. If the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output voltage in regulation. Frequency Synchronization The internal oscillator of the LTC3414 can be synchronized to an external clock connected to the SYNC/MODE pin. The frequency of the external clock can be in the range of 300kHz to 4MHz. For this application, the oscillator timing resistor should be chosen to correspond to a frequency that is 25% lower than the synchronization frequency. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-channel MOSFET and the inductor. Low Supply Operation The LTC3414 is designed to operate down to an input supply voltage of 2.25V. One important consideration at low input supply voltages is that the RDS(ON) of the P-channel and N-channel power switches increases. The user should calculate the power dissipation when the LTC3414 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the LTC3414, however, slope compensation recovery is implemented to keep the maximum inductor peak current constant throughout the range of duty cycles. This keeps the maximum output current relatively constant regardless of duty cycle. Short-Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. To prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. If the inductor valley current increases larger than 7.8A, the top power MOSFET will be held off and switching cycles will be skipped until the inductor current is reduced. 3414f U During synchronization, the burst clamp is set to 0V, and each switching cycle begins at the falling edge of the clock signal. 7 LTC3414 APPLICATIO S I FOR ATIO The basic LTC3414 application circuit is shown in Figure 1. External component selection is determined by the maximum load current and begins with the selection of the operating frequency and inductor value followed by CIN and COUT. Operating Frequency Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency of the LTC3414 is determined by an external resistor that is connected between pin RT and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: 3.08 * 1011 - 10k f Although frequencies as high as 4MHz are possible, the minimum on-time of the LTC3414 imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 110ns; therefore, the minimum duty cycle is equal to 100 * 110ns * f(Hz). ROSC = Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current IL increases with higher VIN or VOUT and decreases with higher inductance. V V IL = OUT 1- OUT VIN fL Having a lower ripple current reduces the core losses in the inductor, the ESR losses in the output capacitors, and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. () 8 U A reasonable starting point for selecting the ripple current is IL = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: V V L = OUT 1 - OUT fIL(MAX) VIN(MAX) W UU The inductor value will also have an effect on Burst Mode operation. The transition to low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price verus size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Coiltronics, Coilcraft, Toko, and Sumida. 3414f LTC3414 APPLICATIO S I FOR ATIO CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal wave current at the source of the top MOSFET. To prevent large voltage transients from occurring, a low ESR input capacitor sized for the maximum RMS current should be used. The maximum RMS current is given by: IRMS V = IOUT (MAX) OUT VIN VIN -1 VOUT This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, VOUT, is determined by: VOUT 1 IL ESR + 8fC OUT The output ripple is highest at maximum input voltage since IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive U applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Output Voltage Programming The output voltage is set by an external resistive divider according to the following equation: R2 VOUT = 0.8V 1 + R1 The resistive divider allows pin VFB to sense a fraction of the output voltage as shown in Figure 2. VOUT R2 VFB LTC3414 SGND 3414 F02 W UU R1 Figure 2. Setting the Output Voltage 3414f 9 LTC3414 APPLICATIO S I FOR ATIO Burst Clamp Programming If the voltage on the SYNC/MODE pin is less than VIN by 1V, Burst Mode operation is enabled. During Burst Mode Operation, the voltage on the SYNC/MODE pin determines the burst clamp level, which sets the minimum peak inductor current, IBURST, for each switching cycle according to the following equation: 6.9A IBURST = VBURST - 0.383V 0.6V ( ) VBURST is the voltage on the SYNC/MODE pin. IBURST can only be programmed in the range of 0A to 7A. For values of VBURST greater than 1V, IBURST is set at 7A. For values of VBURST less than 0.4V, IBURST is set at 0A. As the output load current drops, the peak inductor currents decrease to keep the output voltage in regulation. When the output load current demands a peak inductor current that is less than IBURST, the burst clamp will force the peak inductor current to remain equal to IBURST regardless of further reductions in the load current. Since the average inductor current is greater than the output load current, the voltage on the ITH pin will decrease. When the ITH voltage drops to 150mV, sleep mode is enabled in which both power MOSFETs are shut off along with most of the circuitry to minimize power consumption. All circuitry is turned back on and the power MOSFETs begin switching again when the output voltage drops out of regulation. The value for IBURST is determined by the desired amount of output voltage ripple. As the value of IBURST increases, the sleep period between pulses and the output voltage ripple increase. The burst clamp voltage, VBURST, can be set by a resistor divider from the VFB pin to the SGND pin as shown in Figure 1. Pulse skipping, which is a compromise between low output voltage ripple and efficiency, can be implemented by connecting pin SYNC/MODEto ground. This sets IBURST to 0A. In this condition, the peak inductor current is limited by the minimum on-time of the current comparator. The lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads, pulse skipping allows only a few switching cycles to be skipped while maintaining the output voltage in regulation. 10 U Frequency Synchronization The LTC3414's internal oscillator can be synchronized to an external clock signal. During synchronization, the top MOSFET turn-on is locked to the falling edge of the external frequency source. The synchronization frequency range is 300kHz to 4MHz. Synchronization only occurs if the external frequency is greater than the frequency set by the external resistor. Because slope compensation is generated by the oscillator's RC circuit, the external frequency should be set 25% higher than the frequency set by the external resistor to ensure that adequate slope compensation is present. Soft-Start The RUN/SS pin provides a means to shut down the LTC3414 as well as a timer for soft-start. Pulling the RUN/SS pin below 0.5V places the LTC3414 in a low quiescent current shutdown state (IQ < 1A). The LTC3414 contains an internal soft-start clamp that gradually raises the clamp on ITH after the RUN/SS pin is pulled above 2V. The full current range becomes available on ITH after 1024 switching cycles. If a longer soft-start period is desired, the clamp on ITH can be set externally with a resistor and capacitor on the RUN/SS pin as shown in Figure 1. The soft-start duration can be calculated by using the following formula: VIN tSS = RSS C SS ln (SECONDS) VIN - 1.8V W UU Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VIN quiescent current and I2R losses. 3414f LTC3414 APPLICATIO S I FOR ATIO The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN; thus, their effects will be more pronounced at higher supply voltages. 2. losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. To obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Thermal Considerations In most applications, the LTC3414 does not dissipate much heat due to its high efficiency. I 2R U However, in applications where the LTC3414 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3414 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: tr = (PD)(JA) where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. For the 20-lead exposed TSSOP package, the JA is 38C/W. The junction temperature, TJ, is given by: TJ = TA + tr where TA is the ambient temperature. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). To maximize the thermal performance of the LTC3414, the exposed pad should be soldered to a ground plane. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD(ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components and output capacitor shown in Figure 1 will provide adequate compensation for most applications. 3414f W UU 11 LTC3414 APPLICATIO S I FOR ATIO Design Example As a design example, consider using the LTC3414 in an application with the following specifications: VIN = 2.7V to 4.2V, VOUT = 2.5V, IOUT(MAX) = 4A, IOUT(MIN) = 100mA, f = 1MHz. Because efficiency is important at both high and low load current, Burst Mode operation will be utilized. First, calculate the timing resistor: - 10k = 298k 1* 106 Use a standard value of 294k. Next, calculate the inductor value for about 40% ripple current at maximum VIN: 2.5V 2.5V L= = 0.63H 1- (1MHz)(1.6A) 4.2V Using a 0.47H inductor results in a maximum ripple current of: 2.5V 2.5V IL = = 2.15A 1- (1MHz)(0.47H) 4.2V ROSC = 3.08 * 1011 COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. For this design, a 22F ceramic capacitor and a 470F tantalum capacitor will be used. CIN should be sized for a maximum current rating of: 2.5V 4.2V IRMS = (4A) - 1 = 1.96ARMS 4.2V 2.5V Decoupling the PVIN and SVIN pins with two 22F capacitors and a 330F tantalum capacitor is adequate for most applications. The burst clamp and output voltage can now be programmed by choosing the values of R1, R2, and R3. The voltage on pin MODE will be set to 0.49V by the resistor divider consisting of R2 and R3. A burst clamp voltage of 0.49V will set the minimum inductor current, IBURST, as follows: 6.9A IBURST = VBURST - 0.383V = 1.23A 0.6V ( ) 12 U If we set the sum of R2 and R3 to 200k, then the following equations can be solved: R2 + R3 = 200k R2 0.8V 1+ = R3 0.49V The two equations shown above result in the following values for R2 and R3: R2 = 78.7k , R3 = 124k. The value of R1 can now be determined by solving the following equation. W UU R1 2.5V = 202.7k 0.8V R1 = 432k 1+ A value of 432k will be selected for R1. Figure 4 shows the complete schematic for this design example. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3414. Check the following in your layout: 1. A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small signal components returning to the SGND pin at one point which is then connected to the PGND pin close to the LTC3414. 2. Connect the (+) terminal of the input capacitor(s), CIN, as close as possible to the PVIN pin. This capacitor provides the AC current into the internal power MOSFETs. 3. Keep the switching node, SW, away from all sensitive small signal nodes. 4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. You can connect the copper areas to any DC net (PVIN, SVIN, VOUT, PGND, SGND, or any other DC rail in your system). 5. Connect the VFB pin directly to the feedback resistors. The resistor divider must be connected between VOUT and SGND. 3414f LTC3414 APPLICATIO S I FOR ATIO U Bottom Figure 3. LTC3414 Layout Diagram PGND 20 C1 10pF X7R CITH 470pF X7R RITH 20k R1 432k PGOOD RPG 100k CIN1 22F X5R 2X VIN 2.7V TO 5V R3 124k R2 78.7k VFB 19 ITH 18 PGOOD 17 SVIN 16 LTC3414 NC NC 15 PVIN 14 L1* 0.47H VOUT 2.5V 4A SW 13 SW 12 PGND 11 COUT2 22F X5R Top RSS 2.2M CSS 1000pF X7R + CIN2*** 330F * VISHAY DALE IHLP-2525CZ-01 ** SANYO POSCAP 4TPD470M *** SANYO POSCAP 6TPB330M Figure 4. 2.5V, 4A Regulator at 1MHz, Burst Mode Operation W UU 1 ROSC 294k 2 PGND RT 3 SYNC/MODE 4 RUN/SS 5 SGND 6 7 PVIN 8 SW 9 SW + COUT1** 470F 10 PGND 3413 F04 3414f 13 LTC3414 TYPICAL APPLICATIO S 3.3V, 4A Step-Down Regulator at 1MHz, Forced Continuous Mode CC 100pF X7R CITH 470pF X7R RITH 12.1k * MURATA LQH66SNR68M03L ** TDK C4532X5ROJ107M *** SANYO POSCAP 6TPE150M 2.5V, 4A Step-Down Regulator at 1.25MHz, Synchronized to an External Clock CC 100pF X7R CITH 470pF X7R RITH 12.1k R1 422k * VISHAY DALE IHLP-2525CZ-01 ** TDK C4532X5ROJ107M *** SANYO POSCAP 4TPB220M 14 U 1 ROSC 294k 2 PGND PGND 20 R2 200k RT VFB 19 3 RSS 2.2M CSS 1000pF X7R SYNC/MODE ITH 18 R1 634k C1 22pF X7R PGOOD 4 RUN/SS PGOOD 17 RPG 100k CIN1 22F X5R 2x 5 SGND LTC3414 NC SVIN 16 VIN 5V 6 NC 15 7 PVIN PVIN 14 L1* 0.68H VOUT 3.3V 4A COUT** 100F 2x 8 + SW SW 13 CIN2*** 150F 9 SW SW 12 10 PGND PGND 11 3413 F05 1 ROSC 294k 2 PGND PGND 20 R2 200k RT VFB 19 1.25MHz 3 SYNC/MODE CLOCK RSS 2.2M CSS 1000pF X7R 4 RUN/SS ITH 18 C1 22pF X7R PGOOD PGOOD 17 RPG 100k CIN1** 100F 2x 5 SGND LTC3414 NC SVIN 16 VIN 3.3V 6 NC 15 7 PVIN PVIN 14 L1* 0.47H VOUT 2.5V 4A COUT** 100F 2x 8 + SW SW 13 CIN2*** 220F 9 SW SW 12 10 PGND PGND 11 3413 F06 3414f LTC3414 PACKAGE DESCRIPTIO 4.95 (.195) 6.60 0.10 4.50 0.10 SEE NOTE 4 RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0 - 8 0.09 - 0.20 (.0036 - .0079) 0.45 - 0.75 (.018 - .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CA 6.40 - 6.60* (.252 - .260) 4.95 (.195) 20 1918 17 16 15 14 13 12 11 2.74 (.108) 0.45 0.05 1.05 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 1.20 (.047) MAX 2.74 6.40 (.108) BSC 0.65 (.0256) BSC 0.195 - 0.30 (.0077 - .0118) 0.05 - 0.15 (.002 - .006) FE20 (CA) TSSOP 0203 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3414f 15 LTC3414 TYPICAL APPLICATIO * PULSE P1166.68IT ** SANYO POSCAP 4TPD470M RELATED PARTS PART NUMBER LT1616 LT1676 LT1765 LTC1879 LTC3405/LTC3405A LTC3406/LTC3406B LTC3407 LTC3411 LTC3412 LTC3413 LTC3430 LTC3440/LTC3441 DESCRIPTION 500mA (IOUT), 1.4MHz, High Efficiency Step-Down DC/DC Converter 450mA (IOUT), 100kHz, High Efficiency Step-Down DC/DC Converter 25V, 2.75A (IOUT), 1.25MHz, High Efficiency Step-Down DC/DC Converter 1.20A (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter Dual 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 3A (IOUT Sink/source), 2MHz, Monolithic Synchronous Regulator for DDR/QDR Memory Termination 60V, 2.75A (IOUT), 200kHz, High Efficiency Step-Down DC/DC Converter 600mA/1A (IOUT), 2MHz/1MHz, Synchronous Buck-Boost DC/DC Converter COMMENTS 90% Efficiency, VIN: 3.6V to 25V, VOUT: 1.25V, IQ: 1.9mA, ISD: <1A, ThinSOT Package 90% Efficiency, VIN: 7.4V to 60V, VOUT: 1.24V, IQ: 3.2mA, ISD: 2.5A, S8 Package 90% Efficiency, VIN: 3V to 25V, VOUT: 1.2V, IQ: 1mA, ISD: 15A, S8, TSSOP16E Packages 95% Efficiency, VIN: 2.7V to 10V, VOUT: 0.8V, IQ: 15A, ISD: <1A, TSSOP16 Package 95% Efficiency, VIN: 2.75V to 6V, VOUT: 0.8V, IQ: 20A, ISD: <1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT: 0.6V, IQ: 20A, ISD: <1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT: 0.6V, IQ: 40A, ISD: <1A, MS Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT: 0.8V, IQ: 60A, ISD: <1A, MS Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT: 0.8V IQ: 60A, ISD: <1A, TSSOP16E Package 90% Efficiency, VIN: 2.25V to 5.5V, VOUT: VREF/2, IQ: 280A, ISD: <1A, TSSOP16E Package 90% Efficiency, VIN: 5.5V to 60V, VOUT: 1.2V, IQ: 2.5mA, ISD: 25A, TSSOP16E Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT: 2.5V, IQ: 25A/50A, ISD: <1A, MS Package 3414f LT/TP 1003 1K * PRINTED IN USA 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U 1.5V, 4A Step-Down Regulator at 1MHz, Burst Mode CC 100pF X7R R2 200k 1 ROSC 294k 2 3 RSS 2.2M CSS 1000pF, X7R 4 5 6 7 PGND RT SYNC/MODE RUN/SS SGND LTC3414 NC PVIN SW SW PGND NC PVIN SW SW PGND PGND VFB ITH 20 19 18 17 16 15 14 13 12 11 RPG 100k CIN1 22F X5R 2x CITH 470pF X7R RITH 15k R1 178k C1 39pF X7R PGOOD VIN 2.5V PGOOD SVIN + 8 CIN2** 470F 9 10 L1* 0.44H VOUT 1.5V 4A COUT2 22F X5R + COUT1** 470F 3413 TA01 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2003 |
Price & Availability of LTC3414EFE
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |